Chair of Computer Engineering



The Computer Engineering group is working on design and analysis methods for complex micro- and nanoelectronic circuits and systems. Our specific focus is on such aspects as reliability, dependability, robustness and energy efficiency. Below, please find more details on our current research foci including funded projects, most relevant cooperations, and selected publications.

Low-Power Design and its Implications on Reliability

Energy-efficiency is a key requirement for today’s electronics. Low energy consumption is achieved by techniques such as lowering the supply voltage, switching off blocks that are temporary not in use, and using special low-power transistors. These techniques typically lower the noise margins and make the circuit more vulnerable to external disturbances. On the other hand, improving a circuit’s reliability necessitates redundant structures, which in turn consume energy.

We investigate the relation between low-power design and reliability. One focal point are detection strategy for complex interactions between the logic part of a circuit and its power distribution network. Failure mechanisms such as IR drop, ground bounce and power droop have historically not been a concern on chip level and have been handled on board level. In the recent technology generations, single blocks or even logic gates are subject to these phenomena which cannot be identified by traditional methods. One further topic is the ultra-low-power technique of „Adaptive Voltage Overscaling“ (AVOS). By an aggressive voltage control, we observed energy savings of 20 to 30 percent for image processing applications, at virtually no quality impact.


Selected Publikations

I. Polian. Power supply noise: causes, effects, and testing. ASP Jour. Low-Power Electronics 6(2):326–338, 2010. PDF (Amer Sci Pub)

P. Krause and I. Polian. Adaptive voltage over-scaling for resilient applications. Design Automation and Test in Europe (DATE), Grenoble, France, 2011 (Accepted).

Design of Robust Systems

The continued scaling of structure dimensions makes the hardware blocks more and more vulnerable to errors. Classical fault-tolerance techniques often cannot be applied in practice due to their prohibitive costs and elevated energy consumption. Consequently, the handling of faults must be done by a combination of hardware, software, and system-level techniques. In some applications, it is even acceptable to correct only the most critical errors while leaving non-critical errors uncorrected. For instance, a non-critical error in an imaging application could just slightly modify several pixels of the image calculated by the chip, and the human end-user would not perceive this modification.

We are working on selective hardening strategies which trade off between hardening costs and the error rate achieved. This technique is very well suited to be combined with software fault tolerance, thus allowing the designer to co-optimize system cost, error rate, and performance. Moreover, we study which errors in the system should be classified as critical. In the past, we introduced both application-specific definitions (including Cognitive Resilience for image processing applications) and the generic concept of the Transient-Error Tolerance. We are currently working on similar questions in the field of Probabilistic Robotics.

Funded Projects:


Selected Publications:

I. Polian, J.P. Hayes, S. Reddy, and B. Becker. Modeling and mitigating transient errors in logic circuits IEEE Trans. Dependable and Secure Computing. Accepted. PDF (IEEE PrePrint)

V. Izosimov, I. Polian, P. Pop, P. Eles, and Z. Peng. Analysis and optimization of fault-tolerant embedded systems with hardened processors. Design Automation and Test in Europe (DATE), Nice, France, 2009. PDF (IEEEXplore)

D. Nowroth, I. Polian, and B. Becker. A study of cognitive resilience in a JPEG compressor. , IEEE/IFIP Int'l Conf. on Dependable Systems and Networks (DSN), Anchorage, AK, USA, 2008. PDF (IEEEXplore)

Nanoelectronic Circuits and Architectures

The exponential growth of the integration density cannot be sustained indefinitely. Today’s semiconductor-based technologies will, sooner or later, require a successor. Possible next-generation technologies are to be found in the field of nanotechnology. We are considering several classes of nano devices and study architectures of circuits on their basis. Instances are reversible circuits, which are a special case of quantum circuits, and NanoPLAs, which can be seen as structured arrays of reconfigurable nano devices. Furthermore, we are working on probabilistic aspects of several nanotechnologies, in particular of quantum and stochastic computers.


  • John P. Hayes (University of Michigan, Ann Arbor) – Collaboration supported by the Humboldt Research Award for Prof. Hayes
  • Wenjing Rao (University of Illinois, Chicago)

Selected Publications:

I. Polian, J.P. Hayes, T. Fiehn, and B. Becker. A family of logical fault models for reversible circuits. IEEE Asian Test Symp., Kolkata, India, 2005. PDF (IEEEXplore)

I. Polian and W. Rao. Selective hardening of NanoPLA circuits. IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, Cambridge, MA, 2008. PDF (IEEEXplore)